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TECHNICAL DATA
KK74HCT20A
Dual 4-Input NAND Gate
High-Performance Silicon-Gate CMOS
The KK74HCT20A is identical in pinout to the LS/ALS20. The KK74HCT20A may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. * TTL/NMOS-Compatible Input Levels * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 4.5 to 5.5 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION KK74HCT20AN Plastic KK74HCT20AD SOIC TA = -55 to 125 C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
NC = NO CONNECTION
PIN 14 =VCC PIN 7 = GND PINS 3,11 = NO CONNECTION
FUNCTION TABLE
Inputs A L X X X H B X L X X H C X X L X H D X X X L H Output Y H H H H L
X = don't care
1
KK74HCT20A
MAXIMUM RATINGS*
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, tf Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) Min 4.5 0 -55 0 Max 5.5 VCC +125 500 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
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KK74HCT20A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Symbol Parameter Test Conditions V Guaranteed Limit 25 C to -55C 2.0 2.0 0.8 0.8 4.4 5.4 3.98 0.1 0.1 0.26 0.1 2.0 85 C 2.0 2.0 0.8 0.8 4.4 5.4 3.84 0.1 0.1 0.33 1.0 20 125 C 2.0 2.0 0.8 0.8 4.4 5.4 3.7 0.1 0.1 0.4 1.0 40 A A V Unit
VIH VIL VOH
Minimum HighLevel Input Voltage Maximum Low Level Input Voltage Minimum HighLevel Output Voltage
VOUT=0.1 V or VCC-0.1 V IOUT 20 A VOUT=0.1 V or VCC-0.1 V IOUT 20 A VIN= VIH or VIL IOUT 20 A VIN= VIH or VIL IOUT 4.0 mA
4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5
V V V
VOL
Maximum LowLevel Output Voltage
VIN=VIH IOUT 20 A VIN=VIH IOUT 4.0 mA
IIN ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Quiescent Additional Supply Current
VIN=VCC or GND VIN=VCC or GND IOUT=0A VIN=2.4 V,Any One Input VIN=VCC or GND, Other Inputs IOUT=0A
ICC
-55 C
25 C to 125C 2.4
mA
5.5
2.9
3
KK74HCT20A
AC ELECTRICAL CHARACTERISTICS (VCC =5.0 V 10%,CL=50pF,Input tr=tf=6.0 ns)
Guaranteed Limit Symbol Parameter 25 C to -55C 28 15 10 85C 125C Unit
tPLH, tPHL tTLH, tTHL CIN
Maximum Propagation Delay, Input A ,B,C or D to Output Y (Figures 1 and 2) Maximum Output Transition Time, Any Output (Figures 1 and 2) Maximum Input Capacitance Power Dissipation Capacitance (Per Gate)
35 19 10
42 22 10
ns ns pF
Typical @25C,VCC=5.0 V 29 pF
CPD
Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
Figure 1. Switching Waveforms
Figure 2. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/2 of the Device)
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KK74HCT20A
N SUFFIX PLASTIC DIP (MS - 001AA)
A 14 8 B 1 7
Dimension, mm Symbol A B C MIN 18.67 6.1 MAX 19.69 7.11 5.33 0.36 1.14 2.54 7.62 0 2.92 7.62 0.2 0.38 10 3.81 8.26 0.36 0.56 1.78
F
L
D F
C -T- SEATING N G D 0.25 (0.010) M T K
PLANE
G H
H J
M
J K L M N
NOTES: 1. Dimensions "A", "B" do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side.
D SUFFIX SOIC (MS - 012AB) Dimension, mm
8
A 14
Symbol A
MIN 8.55 3.8 1.35 0.33 0.4 1.27 5.27 0 0.1 0.19 5.8 0.25
MAX 8.75 4 1.75 0.51 1.27
H
B
P
B C
1
G
7 C R x 45
D F G
-TD 0.25 (0.010) M T C M K
SEATING PLANE
H
J F M
J K M P R
8 0.25 0.25 6.2 0.5
NOTES: 1. Dimensions A and B do not include mold flash or protrusion. 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B 0.25 mm (0.010) per side.
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